The avionics architecture presently used in aircraft is based on the specifications according to Arinc 700. According to these specifications, manufacturers of avionics devices provide a specially tailored controller that is accommodated in a line replaceable unit (LRU) for each function. Each LRU thus comprises the following components: power supply, processor, I/O modules and others.
With the use of integrated modular avionics, improved integration by utilising the computing power of microprocessors for several tasks (resource sharing) becomes possible. A reduction in the number of components, and standardisation of components are further advantages.
A known IMA-(integrated modular avionics) architecture provides several cabinets at various locations in the aircraft. For data exchange all models are interconnected by way of a backplane bus (Arinc 659, currently SAFEbus by Honeywell).
Sensor data of the various functions are fed to the core processor by way of the input modules and the backplane bus. In the core processor, an operating system determines which system software (application) is to be used at what time. The data is directly transmitted to the associated software. After completion of processing, the data is returned via the backplane bus to the output module from where it is transmitted to actuators or other systems.
The cabinets in turn are interconnected in a network (Arinc 629).
In this solution the backplane bus represents a bottleneck. In order to prevent a collapse, the data has to be determined deterministically for transmission.
Several attempted solutions for managing these problems are known. For example, in U.S. Pat. No. 5,506,963 a real-time processor system is implemented in that a coprocessor is used which manages the time slices of a specified timeframe for the processor. These time slices can be of different duration, with allocation to one or several installed layouts being determined by the function/application. In this solution a central databus is used with deterministic data traffic. Tools for setting up the data traffic are necessary, data conflicts can arise, and changes in the function are only possible if at the same time the bus data structure is adapted.
According to U.S. Pat. No. 4,658,359 a computer is used to manage a plurality of computers in a complex avionics system. A single user can thus process a plurality of functions/applications from one display screen. Here, operation and modification of applications of a communication system by means of an executive computer are in the foreground. The use as an integrated modular avionics system with transputers is not considered.
According to U.S. Pat. No. 5,361,367 a number of single-instruction multiple data (SIMD) processors are accommodated in a computer. Two sets of respectively three individual processors are controlled by a master computer and are connected to a plurality of registers. These SIMD processors are linked, for data exchange, to form a ring arrangement or pipeline arrangement. This is a high-speed processor. However, the data bus problems at high data rates and in the case of distributed tasks remain.
According to EP 0,570,729 A2 an individual chip houses eight processors that are linked by way of a cube topology. Compared to conventional microprocessors there are fewer pins, and the memory time is shortened. Here again, the solution shows an improved high-speed processor chip.